This application claims the priority benefit of Taiwan application serial no. 92112792, filed May 12, 2003.
1. Field of the Invention
The present invention relates to a low-temperature polysilicon (LTPS) thin film transistor (TFT). More particularly, the present invention relates to a complementary metal oxide semiconductor (CMOS) transistor consisting of two LTPS TFTs of different conductivity types, and a semiconductor device based on the CMOS transistor.
2. Description of the Related Art
With advances of high technologies, video products, especially digital video/image apparatuses, have been widely used in daily life. In a digital video/image apparatus, the display device is surely an important component for displaying information. A user can read the information from the display device, and may further operate the apparatus according to the information.
The hottest display product in recent years is no other than the liquid crystal display (LCD), especially the TFT-LCD utilizing active-matrix driving mechanism. In the field of TFT, the polysilicon-based TFT has been studied in much effort for possessing an electron mobility much larger than that of a conventional xe2x96xa1-Si TFT. Therefore, polysilicon TFTs can be made smaller to increase the aperture ratio of the pixel and thereby enhance the brightness of the LCD. In other words, using polysilicon TFTs in a LCD consumes less energy when the same brightness is achieved. Moreover, because polysilicon has high electron mobility, the driving devices of a LCD can also be formed on the glass substrate within the polysilicon TFT process. Therefore, the performance and the reliability of a LCD panel can be improved, and the cost for fabricating a LCD panel or a LCD monitor is lowered. In addition, a polysilicon-TFT LCD is thin, light, and has a higher resolution, and is therefore particularly applicable to a mobile terminal product that requires weight reduction and electricity saving.
In the beginning, a poly-Si TFT is fabricated with a solid-phase crystallization (SPC) process, wherein the temperature is up to 1000xc2x0 C. and a quartz substrate having a high melting point is required. However, since quartz is much more expensive than glass and the size of a quartz substrate is restricted to 2-3 inches, only a small-sized poly-Si TFT-LCD can be made with this method. To solve this problem, the so-called low-temperature polysilicon (LTPS) TFT process is provided, using laser crystallization or excimer laser annealing (ELA) to convert an xe2x96xa1-Si film into a poly-Si film. Since the temperature of an LTPS-TFT process is lower than 600xc2x0 C., a glass substrate generally used in an xe2x96xa1-Si TFT-LCD can be used to fabricate a larger LCD panel.
In addition, since polysilicon has higher electron mobility, the driving devices of a LCD can be formed synchronously on the glass substrate around the display area during the LTPS-TFT process. FIGS. 1A-1B illustrate a CMOS transistor as an example of such LCD driving devices, wherein FIG. 1A illustrates a top view of a conventional CMOS transistor including an N-type LTPS TFT and a P-type LTPS TFT, and FIG. 1B illustrates a cross-sectional view of the CMOS transistor in FIG. 1A along line I-Ixe2x80x2.
Referring to FIGS. 1A-1B, a conventional CMOS transistor 10 includes an N-type LTPS TFT 110 and a P-type LTPS TFT 120 disposed on a substrate 100. The N-type LTPS TFT 110 includes a gate 102 and a polysilicon island 104 between the gate 102 and the substrate 100, wherein the polysilicon island 104 includes a channel region 105 and a doped region 106a and a drain region 106b beside the channel region 105. The P-type LTPS TFT 120 includes a gate 112 and a polysilicon island 114 between the gate 112 and the substrate 100, wherein the polysilicon island 114 includes a channel region 115 and a source region 116a and a doped region 116b beside the channel region 115. The N-type LTPS TFT 110 and the P-type LTPS TFT 120 are covered by an inter-layer dielectric layer 130, and the doped region 106a of the N-type LTPS TFT 110 and the doped region 116b of the P-type LTPS TFT 120 are electrically connected via two contacts 132 through the inter-layer dielectric layer 130 and a conductive line 122.
The polysilicon island 104/114 is isolated from the gate 102/112 by a gate insulating film 124, and is separated from the substrate 100 by a buffer layer 126. In the N-type LTPS TFT 110, a lightly doped drain (LDD) region 107 is located between the channel region 105 and the doped region 106a/drain region 106b. In addition, source/drain contact metals 128 are disposed connecting with the source region 116a and the drain region 106b. 
As shown by the CMOS transistor layout in FIG. 1A, since the N-type LTPS TFT 110 and the P-type LTPS TFT 120 are arranged in series in the lateral direction, the doped region 106a of the N-type LTPS TFT 110 and the doped region 116b of the P-type LTPS TFT 120 are separated by a minimal distance in the lateral direction. Consequently, when the contact 132 in FIG. 1A has a width/length of 6xe2x96xa1m/6xe2x96xa1m, for example, the overall width 142 of the CMOS transistor 10 is up to about 56xe2x96xa1m because of the design rule. Since the minimal width of a conventional CMOS transistor is large, the conventional CMOS layout is not suitable for a planar display having a reduced pixel size and a higher resolution.
In view of the foregoing, this invention provides a CMOS transistor and a semiconductor device based on the CMOS transistor to decrease the layout width, so that the peripheral area of a glass substrate is sufficient for forming CMOS-based driving devices when the resolution of the display area is increased.
The CMOS transistor of this invention includes a first TFT of a first conductivity type, a second TFT of a second conductivity type, an inter-layer dielectric layer, a conductive line, a source contact metal and a drain contact metal. The first TFT includes a first gate and a first polysilicon island under the first gate, wherein the first polysilicon island includes a first channel region right under the first gate, a source region on one side of the first gate, and a first doped region of a first conductivity type on the other side of the first gate. The source region, the first channel region and the first doped region are arranged along a first direction. The second TFT includes a second gate and a second polysilicon island under the second gate, wherein the second polysilicon island includes a second channel region right under the second gate, a second doped region of a second conductivity type on one side of the second gate, and a drain region on the other side of the second gate. The second doped region, the second channel region and the drain region are arranged along the first direction, and the second doped region and the first doped region are arranged along a second direction that is perpendicular to the first direction. The inter-layer dielectric layer covers the first TFT and the second TFT, and has a plurality of contacts therein connecting with the first doped region and the second doped region. The conductive line is disposed on the inter-layer dielectric layer extending along the second direction, and electrically connects the first doped region and the second doped region via the contacts. The source contact metal is disposed on and through the inter-layer dielectric layer to electrically connect with the source region, and the drain contact metal on and through the inter-layer dielectric layer to electrically connect with the drain region.
The CMOS-based device of this invention includes at least one first LTPS TFT of a first conductivity type, second LTPS TFTs of a second conductivity type, an inter-layer dielectric layer, conductive lines and source/drain contact metals. The first LTPS TFT is arranged parallel to the second LTPS TFTs with a displacement relative to each of the second LTPS TFTS, and includes a first gate line and a first polysilicon island under the first gate line. The first polysilicon island includes a first channel region right under the first gate line, a first doped region on one side of the first gate line, and a second doped region on the other side of the first gate line. Each of the second LTPS TFTs includes a second gate line and a second polysilicon island under the second gate line, wherein the second polysilicon island includes a second channel region right under the second gate line, a third doped region on one side of the second gate line, and a source/drain region on the other side of the second gate line. The inter-layer dielectric layer covers the first TFT and the second TFTs, and has contacts therein connecting with the first doped region, the second doped region and the third doped region, respectively. Each conductive line is disposed on the inter-layer dielectric layer extending substantially parallel to the first gate line and the second gate line, and electrically connects the first (or second) doped region and a third doped region via the contacts. A source/drain contact metal is disposed on and through the inter-layer dielectric layer to electrically connect with a source/drain region.
Since the first LTPS TFT and the second LTPS TFT in a CMOS transistor of this invention are arranged in parallel with a relative displacement in the first direction, the overall width of the CMOS transistor or the CMOS-based device can be remarkably reduced to apply to a high-resolution display.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.